Trait libreda_sta::traits::timing_base::TimingBase

pub trait TimingBase: LoadBase {
    type Signal: Signal<LogicValue = Self::LogicValue>;
    type LogicValue: Copy + Clone + Debug + Default + Sync + Send;
}

Defines the concept of signals (e.g. slew rates and actual arrival times) and output loads (e.g. load capacitance).

Required Associated Types

type Signal: Signal<LogicValue = Self::LogicValue>

Representation of signals at input or output pins. In case of the Non-linear delay model (NDLM) this could be a bundle of the slew rate and the delay but also the polarity of the signal. But this type could as well also be a statistical representation of a signal, e.g. a probability distribution of arrival times.

type LogicValue: Copy + Clone + Debug + Default + Sync + Send

Type of logic value. Typically this might be a three-valued type which represents logical 0, 1 and ‘unknown’. The default is typically ‘unknown’. This is used to specify static input signals when evaluating cell delays or constraints.

Implementors

impl<'a, D> TimingBase for ZeroInterconnectDelayModel<'a, D>where D: TimingBase,

type Signal = <D as TimingBase>::Signal

type LogicValue = <D as TimingBase>::LogicValue

impl<'a, N: NetlistBase> TimingBase for NDLMCellModel<'a, N>

type Signal = NDLMSignal

type LogicValue = Logic3

impl<M> TimingBase for Model<M>where M: TimingBase,

type Signal = SignalClocked<<M as TimingBase>::Signal>

type LogicValue = <M as TimingBase>::LogicValue