// Copyright (c) 2021-2021 Thomas Kramer.
// SPDX-FileCopyrightText: 2022 Thomas Kramer <code@tkramer.ch>
//
// SPDX-License-Identifier: AGPL-3.0-or-later

//! Define base types used for static timing analysis.

use crate::traits::LoadBase;

/// Defines the concept of signals (e.g.  slew rates and actual arrival times) and output loads (e.g. load capacitance).
pub trait TimingBase: LoadBase {
    /// Representation of signals at input or output pins.
    /// In case of the Non-linear delay model (NDLM) this could be a bundle of the slew rate
    /// and the delay but also the polarity of the signal.
    /// But this type could as well also be a statistical representation of a signal, e.g. a probability
    /// distribution of arrival times.
    type Signal: Signal<LogicValue = Self::LogicValue>;

    /// Type of logic value.
    /// Typically this might be a three-valued type which represents logical `0`, `1` and 'unknown'.
    /// The default is typically 'unknown'.
    /// This is used to specify static input signals when evaluating cell delays or constraints.
    type LogicValue: Copy + Clone + std::fmt::Debug + Default + Sync + Send;
}

/// Representation of signals at input or output pins.
pub trait Signal: Clone + std::fmt::Debug + Sync + Send {
    /// Type of logic value.
    /// Typically this might be a three-valued type which represents logical `0`, `1` and 'unknown'.
    /// The default is typically 'unknown'.
    /// This is used to specify static input signals when evaluating cell delays or constraints.
    type LogicValue: Copy + Clone + std::fmt::Debug + Default + Sync + Send;

    /// Get the target value of a signal.
    fn logic_value(&self) -> Self::LogicValue;
}