Crate libreda_sta

Incremental graph-based static timing analysis (STA) for the LibrEDA framework.

Timing analysis is performed on netlist data structures that implement the [trait@NetlistBase] trait. This makes the STA algorithm easily portable.

The concept of timing, delays and constraints is abstracted by a set of traits. This architecture should allow to implement simple timing models such as the non-linear delay model (NDLM) and more complicated models (such as statistical models) in a consistent way.

Modules

• cone_propagation 🔒
  Propagate forward and backward cones from a set of frontier nodes. The cones mark the regions where the timing must potentially be updated.
• graphviz 🔒
  Dump the timing graph in the graphviz ‘dot’ format.
• levelization 🔒
  Graph levelization based on an operator formulation. Compute the level of all graph nodes in a directed acyclic graph. The level of a node is the minimum distance to a node without incoming edges with each edge having a distance of 1.
• liberty_library
  Public modules Interface definitions for cell delay look-up as it is provided for example by Liberty libraries.
• liberty_util 🔒
  Helper functions to interpret the liberty library which comes from the parser.
• models
  Model implementations (cell delay and constraints, interconnect delays).
• signal_propagation 🔒
  Graph levelization based on an operator formulation. Compute the level of all graph nodes in a directed acyclic graph. The level of a node is the minimum distance to a node without incoming edges with each edge having a distance of 1.
• timing_graph 🔒
  Construct timing graphs (delay graph, constraint graph) from a netlist.
• traits
  Traits for abstracting timing models.

Structs

• ClockDefinition
  Definition of a clock source.
• Constraint 🔒
• ConstraintArcType
  Public exports. Type of a constraint arc.
• Modifiable
  Marker type. The timing computation is out of date. Timing queries are disabled but modifications are enabled.
• PrecomputedOutputLoads 🔒
• SimpleSTA
  Simple static timing analysis engine.
• TimingAvailable
  Marker type. The timing is computed. Timing queries are allowed but no modifications are allowed unless the state is changed to Modifiable.

Enums

• ConstraintClass
  Public exports. Type of a timing constraint.
• EdgePolarity
  Public exports. Type of a signal edge. Either rising (0->1), falling (1->0).
• SignalTransition
  Public exports. Type of a signal edge. Either rising (0->1), falling (1->0) or both of them.
• StaError
  Error during static timing analysis. This includes errors in the liberty library, mismatches between netlist and library or invalid netlists (drive conflicts, etc).
• StaMode
  Analysis mode.

Constants

• PATH_SEPARATOR 🔒

Traits

• SimpleSTAState
  Marker trait.
• TimingLibrary
  Public exports. Query cell delays and setup/hold constraints.

Functions

• compute_net_loads 🔒
  Compute total net capacitances for each net of the top circuit. Simply sums up the input capacitances of all connected input pins for each net.