Struct libreda_sta::models::ndlm_cell_delay::NDLMCellModel

pub struct NDLMCellModel<'a, N: NetlistBase> {
    sta_mode: StaMode,
    delay_model_type: DelayModelType,
    library: &'a LibertyTimingLibrary<'a>,
    pin_capacitances: FnvHashMap<N::PinId, NDLMOutputLoad>,
    pin_data: FnvHashMap<N::PinId, &'a Pin>,
    ordered_pins: FnvHashMap<N::CellId, Vec<N::PinId>>,
    warn_negative_slew: Once,
    warn_negative_delay: Once,
}

Parameters

'a: Lifetime of the liberty library.

Fields

sta_mode: StaMode

delay_model_type: DelayModelType

Choose between using NDLM or a constant delay.

library: &'a LibertyTimingLibrary<'a>

pin_capacitances: FnvHashMap<N::PinId, NDLMOutputLoad>

Table for quickly finding the input capacitance of a pin. Capacitance is available also in pin_data but access might be faster using this field.

pin_data: FnvHashMap<N::PinId, &'a Pin>

Lookup-table for pin data (capacitance, delay arcs, constraint arcs, …).

ordered_pins: FnvHashMap<N::CellId, Vec<N::PinId>>

Cache the pin ordering for all the cells.

warn_negative_slew: Once

Warn once about negative slew.

warn_negative_delay: Once

Implementations

impl<'a, N: NetlistBase> NDLMCellModel<'a, N>

pub fn new(library: &'a LibertyTimingLibrary<'_>, netlist: &N) -> Self

Create a new NDLM cell model based on a liberty library.

pub fn set_delay_model_type(&mut self, model_type: DelayModelType)

Choose between NDLM and constant delays.

fn init(&mut self, netlist: &N)

fn init_capacitance_table(&mut self, netlist: &N)

Create a lookup-table for the default pin capacitances.

Trait Implementations

impl<'a, N: NetlistBase> CellConstraintModel<N> for NDLMCellModel<'a, N>

fn get_required_input( &self, netlist: &N, constrained_pin: &N::PinId, constrained_pin_signal: &Self::Signal, related_pin: &N::PinId, related_pin_signal: &Self::Signal, _other_inputs: &impl Fn(&N::PinId) -> Option<Self::Signal>, output_loads: &impl Fn(&N::PinId) -> Option<Self::Load> ) -> Option<Self::RequiredSignal>

Compute the constraint on the constrained_pin imposed by the related_pin. Returns None if there’s no such constraint.

fn constraint_arcs( &self, netlist: &N, cell_id: &N::CellId ) -> Box<dyn Iterator<Item = CellConstraintArc<N::PinId>> + '_>

Get all constraint arcs in the given cell.

impl<'a, N: NetlistBase> CellDelayModel<N> for NDLMCellModel<'a, N>

fn cell_output( &self, netlist: &N, input_pin: &N::PinId, input_signal: &Self::Signal, output_pin: &N::PinId, output_load: &Self::Load, _other_inputs: &impl Fn(&N::PinId) -> Option<Self::LogicValue> ) -> Option<Self::Signal>

Propagate a signal from the input_pin to the output_pin. This is used as a more general form of computing the cell delay. The input_pin and the output_pin must be pins of the same cell.

fn delay_arcs( &self, netlist: &N, cell: &N::CellId ) -> Box<dyn Iterator<Item = CellDelayArc<N::PinId>> + '_>

Iterate over the output pins of all delay arcs starting at related_pin.

fn delay_arcs_from_pin( &self, netlist: &N, input_pin: &N::PinId ) -> Box<dyn Iterator<Item = N::PinId> + '_>

Iterate over the output pins of all delay arcs starting at related_pin.

fn delay_arcs_reversed( &self, output_pin: &N ) -> Box<dyn Iterator<Item = N::PinId>>

Iterate over the related pins of all delay arcs ending at output_pin.

impl<'a, N: NetlistBase> CellLoadModel<N> for NDLMCellModel<'a, N>

fn input_pin_load( &self, input_pin: &N::PinId, _other_inputs: &impl Fn(&N::PinId) -> Option<Self::LogicValue> ) -> Self::Load

Get the load created by a pin, typically its capacitance.

fn zero(&self) -> Self::Load

Return a value representing no load at all (zero capacitance for example).

impl<'a, N: NetlistBase> CellModel<N> for NDLMCellModel<'a, N>

fn ordered_pins(&self, cell: &N::CellId) -> Vec<N::PinId>

Get the cell pins in a consistent ordering. The same ordering will be used for passing input signals to the cell delay model or cell constraint model.

impl<'a, N: NetlistBase> ConstraintBase for NDLMCellModel<'a, N>

type Constraint = NDLMConstraint

Representation of a constraint. This might be for example an earliest or latest required arrival time or a allowed timing window or also a constraint on any other signal properties such as the slew.

type RequiredSignal = NDLMRequiredSignal

Representation of a signal which is required to satisfy constraints.

type Slack = NDLMSlack

Difference between the arrival times of an actual signal and a required signal.

fn summarize_constraints( &self, s1: &Self::RequiredSignal, s2: &Self::RequiredSignal ) -> Self::RequiredSignal

Summarize two constraints c1 and c2 into a single constraint c such that if c is satisfied then also c1 and c2 are satisfied. Depending on the timing analysis mode (late/early) this might be a max or min function.

fn solve_delay_constraint( &self, actual_delay: &Self::Delay, required_output: &Self::RequiredSignal, _actual_input: &Self::Signal ) -> Self::RequiredSignal

Find the required input signal such that the actual output signal is equal to the required_output. The actual_delay from the input to the output is given. Also the actual output is given (might not be necessary to compute the result).

fn get_slack( &self, actual_signal: &Self::Signal, required_signal: &Self::RequiredSignal ) -> Self::Slack

Compute the slack between the actual signal and the required signal. Positive slack implies a met timing. Negative slack implies a violated timing.

impl<'a, N: Debug + NetlistBase> Debug for NDLMCellModel<'a, N>where N::PinId: Debug, N::CellId: Debug,

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl<'a, N: NetlistBase> DelayBase for NDLMCellModel<'a, N>

type Delay = NDLMDelay

Type representing a delay. This can be as simple as a f64 or more complicated such as a probability distribution.

fn summarize_delays(&self, a: &Self::Signal, b: &Self::Signal) -> Self::Signal

Summarize multiple possible output signals into one signal. Depending on the timing analysis mode (late/early) this might be a max or min function.

fn get_delay(&self, from: &Self::Signal, to: &Self::Signal) -> Self::Delay

Compute the delay from one signal to another signal.

impl<'a, N: NetlistBase> LoadBase for NDLMCellModel<'a, N>

type Load = NDLMOutputLoad

An electrical load. Typically a capacitance.

fn sum_loads(&self, load1: &Self::Load, load2: &Self::Load) -> Self::Load

Compute the sum of two loads.

impl<'a, N: NetlistBase> TimingBase for NDLMCellModel<'a, N>

type Signal = NDLMSignal

Representation of signals at input or output pins. In case of the Non-linear delay model (NDLM) this could be a bundle of the slew rate and the delay but also the polarity of the signal. But this type could as well also be a statistical representation of a signal, e.g. a probability distribution of arrival times.

type LogicValue = Logic3

Type of logic value. Typically this might be a three-valued type which represents logical 0, 1 and ‘unknown’. The default is typically ‘unknown’. This is used to specify static input signals when evaluating cell delays or constraints.