Struct libreda_sta::models::zero_interconnect_delay::ZeroInterconnectDelayModel

pub struct ZeroInterconnectDelayModel<'a, D> {
    delay_model: &'a D,
}

Interconnect delay model which reports zero delay for a source and target terminal which belong to the same net and ‘no delay’ if the terminals don’t belong to the same net.

Fields

delay_model: &'a D

Implementations

impl<'a, D> ZeroInterconnectDelayModel<'a, D>

pub fn new(delay_model: &'a D) -> Self

Create a new interconnect delay model which returns a zero-delay for each interconnect. The model derives the data types for delays from the supplied delay_model.

Trait Implementations

impl<'a, D> DelayBase for ZeroInterconnectDelayModel<'a, D>where D: DelayBase,

Delegate DelayModel implementation to self.delay_model.

type Delay = <D as DelayBase>::Delay

Type representing a delay. This can be as simple as a f64 or more complicated such as a probability distribution.

fn summarize_delays( &self, signal1: &Self::Signal, signal2: &Self::Signal ) -> Self::Signal

Summarize multiple possible output signals into one signal. Depending on the timing analysis mode (late/early) this might be a max or min function.

fn get_delay(&self, from: &Self::Signal, to: &Self::Signal) -> Self::Delay

Compute the delay from one signal to another signal.

impl<'a, D, N: NetlistBase> InterconnectDelayModel<N> for ZeroInterconnectDelayModel<'a, D>where D: DelayBase,

fn interconnect_output( &self, netlist: &N, source_terminal: &TerminalId<N>, input_signal: &Self::Signal, target_terminal: &TerminalId<N>, output_load: &Self::Load ) -> Option<Self::Signal>

Compute the cell delay from the source_terminal to the target_terminal.

impl<'a, D> LoadBase for ZeroInterconnectDelayModel<'a, D>where D: LoadBase,

type Load = <D as LoadBase>::Load

An electrical load. Typically a capacitance.

fn sum_loads(&self, load1: &Self::Load, load2: &Self::Load) -> Self::Load

Compute the sum of two loads.

impl<'a, D> TimingBase for ZeroInterconnectDelayModel<'a, D>where D: TimingBase,

type Signal = <D as TimingBase>::Signal

Representation of signals at input or output pins. In case of the Non-linear delay model (NDLM) this could be a bundle of the slew rate and the delay but also the polarity of the signal. But this type could as well also be a statistical representation of a signal, e.g. a probability distribution of arrival times.

type LogicValue = <D as TimingBase>::LogicValue

Type of logic value. Typically this might be a three-valued type which represents logical 0, 1 and ‘unknown’. The default is typically ‘unknown’. This is used to specify static input signals when evaluating cell delays or constraints.