Struct libreda_sta::models::clock_tracking::Model

pub struct Model<M> {
    inner: M,
}

Wrap a delay and/or constraint model and add the capability of tracking clock sources.

Fields

inner: M

Underlying delay/constraint model.

Trait Implementations

impl<M> ConstraintBase for Model<M>where M: ConstraintBase,

type Constraint = <M as ConstraintBase>::Constraint

Representation of a constraint. This might be for example an earliest or latest required arrival time or a allowed timing window or also a constraint on any other signal properties such as the slew.

type RequiredSignal = <M as ConstraintBase>::RequiredSignal

Representation of a signal which is required to satisfy constraints.

type Slack = <M as ConstraintBase>::Slack

Difference between the arrival times of an actual signal and a required signal.

fn summarize_constraints( &self, constraint1: &Self::RequiredSignal, constraint2: &Self::RequiredSignal ) -> Self::RequiredSignal

Summarize two constraints c1 and c2 into a single constraint c such that if c is satisfied then also c1 and c2 are satisfied. Depending on the timing analysis mode (late/early) this might be a max or min function.

fn solve_delay_constraint( &self, actual_delay: &Self::Delay, required_output: &Self::RequiredSignal, actual_signal: &Self::Signal ) -> Self::RequiredSignal

Find the required input signal such that the actual output signal is equal to the required_output. The actual_delay from the input to the output is given. Also the actual output is given (might not be necessary to compute the result).

fn get_slack( &self, actual_signal: &Self::Signal, required_signal: &Self::RequiredSignal ) -> Self::Slack

Compute the slack between the actual signal and the required signal. Positive slack implies a met timing. Negative slack implies a violated timing.

impl<M> DelayBase for Model<M>where M: DelayBase,

type Delay = <M as DelayBase>::Delay

Type representing a delay. This can be as simple as a f64 or more complicated such as a probability distribution.

fn summarize_delays( &self, signal1: &Self::Signal, signal2: &Self::Signal ) -> Self::Signal

Summarize multiple possible output signals into one signal. Depending on the timing analysis mode (late/early) this might be a max or min function.

fn get_delay(&self, from: &Self::Signal, to: &Self::Signal) -> Self::Delay

Compute the delay from one signal to another signal.

impl<M> LoadBase for Model<M>where M: LoadBase,

type Load = <M as LoadBase>::Load

An electrical load. Typically a capacitance.

fn sum_loads(&self, load1: &Self::Load, load2: &Self::Load) -> Self::Load

Compute the sum of two loads.

impl<M> TimingBase for Model<M>where M: TimingBase,

type Signal = SignalClocked<<M as TimingBase>::Signal>

Representation of signals at input or output pins. In case of the Non-linear delay model (NDLM) this could be a bundle of the slew rate and the delay but also the polarity of the signal. But this type could as well also be a statistical representation of a signal, e.g. a probability distribution of arrival times.

type LogicValue = <M as TimingBase>::LogicValue

Type of logic value. Typically this might be a three-valued type which represents logical 0, 1 and ‘unknown’. The default is typically ‘unknown’. This is used to specify static input signals when evaluating cell delays or constraints.