Struct libreda_sta::signal_propagation::PropagationOp

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struct PropagationOp<'a, G, N, D, IC, ICL> {
    netlist: &'a N,
    cell_model: &'a D,
    interconnect_delay_model: &'a IC,
    interconnect_load_model: &'a ICL,
    generation: u32,
    _graph_type: PhantomData<G>,
    _node_data_type: PhantomData<N>,
}

Expand description

Propagate actual signals, constraints and required signals on the full (!) netlist. Requires that all (!) primary inputs of the delay graph are present in the initial worklist. Otherwise the algorithm will miss parts of the graph.

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§netlist: &'a N

Eventually need the netlist to do the mapping from terminals to cells. TODO: remove

§cell_model: &'a D

The cell model provides the timing behaviour of cells (delays, constraints).

§interconnect_delay_model: &'a IC

Model for wire delays.

§interconnect_load_model: &'a ICL

Provides the loads imposed by nets attached to the outputs of logic gates.

§generation: u32

The number of the current iteration. Used to detect nodes which have not yet been touched in the current iteration.

§_graph_type: PhantomData<G>§_node_data_type: PhantomData<N>

Implementations§

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impl<'a, G, N, C, IC, ICL> PropagationOp<'a, G, N, C, IC, ICL>where N: NetlistBase, C: DelayBase + ConstraintBase + CellDelayModel<N> + CellConstraintModel<N>, IC: InterconnectDelayModel<N, Signal = C::Signal>, ICL: InterconnectLoadModel<N, Load = C::Load>, G: GraphBase + Data<NodeWeight = NodeData<N, C>, EdgeWeight = EdgeData<C>> + IntoEdgesDirected + DataMap, G::NodeId: Debug,

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fn new( netlist: &'a N, delay_model: &'a C, interconnect_delay_model: &'a IC, interconnect_load_model: &'a ICL, generation: u32 ) -> Self

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fn evaluate_delay_arc( &self, netlist: &N, local_view: &LocalGraphView<&G, FullConflictDetection>, input_signal: &C::Signal, output_load: &C::Load, graph_edge: G::EdgeRef, other_inputs: &impl Fn(&N::PinId) -> Option<C::LogicValue> ) -> Option<C::Signal>

Propagate the signal along a delay arc. The graph edge represents the delay arc. The delay arc might go from a cell output to a cell input (inter-cell or wiring delay) or the other way from a cell input to a cell output (intra-cell delay).

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fn evaluate_constraint_arc( &self, local_view: &LocalGraphView<&G, FullConflictDetection>, local_data: &SyncNodeData<C>, constraint_edge: G::EdgeRef, other_inputs: &impl Fn(&N::PinId) -> Option<C::Signal>, output_loads: &impl Fn(&N::PinId) -> Option<C::Load> ) -> Option<C::RequiredSignal>

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fn mark_forward_dependency_resolved( &self, local_view: &LocalGraphView<&G, FullConflictDetection>, push_to_worklist: &mut impl FnMut(WorkItem<G::NodeId>) )

Mark this dependency as resolved. Create new activities from output nodes which have all dependencies resolved.

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fn mark_backward_dependency_resolved( &self, local_view: &LocalGraphView<&G, FullConflictDetection>, push_to_worklist: &mut impl FnMut(WorkItem<G::NodeId>) )

Mark this dependency as resolved for backward propagation. Create new activities from output nodes which have all dependencies resolved.

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fn propagate_forward( &self, local_view: &LocalGraphView<&G, FullConflictDetection>, local_data: &mut SyncNodeData<C>, push_to_worklist: impl FnMut(WorkItem<G::NodeId>) ) -> Result<(), DataConflictErr<G::NodeId, G::EdgeId>>

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fn propagate_backward( &self, local_view: &LocalGraphView<&G, FullConflictDetection>, local_data: &mut SyncNodeData<C>, push_to_worklist: impl FnMut(WorkItem<G::NodeId>) ) -> Result<(), DataConflictErr<G::NodeId, G::EdgeId>>

Compute the required signals such that constraints are met. Signal requirements of a node are imposed by outgoing delay arcs and incoming constraint arcs.