Struct libreda_sta::timing_graph::TimingGraph

pub(crate) struct TimingGraph<N: NetlistIds, T: ConstraintBase> {
    pub(crate) arc_graph: StableDiGraph<NodeData<N, T>, EdgeData<T>>,
    pub(crate) aat_source_node: NodeIndex,
    pub(crate) rat_source_node: NodeIndex,
    pub(crate) node2term: FnvHashMap<NodeIndex, TerminalId<N>>,
    pub(crate) term2node: FnvHashMap<TerminalId<N>, NodeIndex>,
    frontier: FnvHashSet<NodeIndex>,
}

Fields

arc_graph: StableDiGraph<NodeData<N, T>, EdgeData<T>>

Graph structure holding all delay and constraint arcs. Their value corresponds to the delay.

aat_source_node: NodeIndex

The source node is used as a starting point for computing the actual arrival times. All primary inputs to the combinational logic are connected to this source node.

rat_source_node: NodeIndex

The source node is used as a starting point for computing the required arrival times. All constrained pins are connected to this source node.

node2term: FnvHashMap<NodeIndex, TerminalId<N>>

Mapping from graph nodes to terminal IDs in the netlist.

term2node: FnvHashMap<TerminalId<N>, NodeIndex>

Mapping from terminal IDs in the netlist to graph nodes.

frontier: FnvHashSet<NodeIndex>

List of nodes from which a timing change originates. They are used to find the forward-cone and backward-code which are subject to change during an incremental update.

Implementations

impl<N: NetlistBase, T: ConstraintBase> TimingGraph<N, T>

pub fn new() -> Self

Create empty timing graph.

pub fn get_node_data( &self, pin: &TerminalId<N> ) -> Option<IdLockReadGuard<'_, SyncNodeData<T>>>

Get read access to the node data. Returns None if the terminal does not exist in the timing graph. Panics, if the read-lock cannot be acquired. Use only while there’s no timing propagation running!

pub fn graph(&self) -> &StableDiGraph<NodeData<N, T>, EdgeData<T>>

Get a reference to the delay graph.

pub fn take_frontier(&mut self) -> FnvHashSet<NodeIndex>

Take the set of frontier nodes and replace it by an empty set.

pub fn add_to_frontier(&mut self, terminal: &TerminalId<N>)

Mark a node which needs to be recomputed in the next incremental update.

pub fn build_from_netlist<C, D>( top_ref: &CellRef<'_, N>, delay_model: &D, constraint_model: &C ) -> Selfwhere D: CellDelayModel<N, Delay = T::Delay>, C: CellConstraintModel<N, Constraint = T::Constraint>,

Assemble a directed graph which represents all delays arcs and constraints (without values yet). Net terminals become nodes in the graph. Cell-internal arcs are derived from the cell_delay_arcs. Inter-cell arcs (interconnects) are derived from the netlist of the top cell top_ref.

pub fn create_cell_instance<C, D>( &mut self, inst: &CellInstRef<'_, N>, delay_model: &D, constraint_model: &C )where D: CellDelayModel<N, Delay = T::Delay>, C: CellConstraintModel<N, Constraint = T::Constraint>,

Create graph nodes for each pin instance.

pub fn remove_cell_instance(&mut self, inst: &CellInstRef<'_, N>)

pub fn remove_net(&mut self, net: &NetRef<'_, N>) -> Result<(), StaError>

Remove all inter-cell arcs created by this net.

pub fn connect_terminal(&mut self, t: TerminalRef<'_, N>, net: Option<N::NetId>)

Disconnect the terminal from the old net and connect it to the new net (if it is Some).

pub fn create_terminal(&mut self, terminal_id: TerminalId<N>)

fn create_pin(&mut self, pin: PinRef<'_, N>)

fn remove_terminal(&mut self, terminal: TerminalId<N>)

pub fn remove_pin(&mut self, pin: N::PinId)

pub fn remove_pin_instance(&mut self, pin: N::PinInstId)

fn create_delay_edges_inter_cell( &mut self, top_ref: &CellRef<'_, N> ) -> Result<(), StaError>

fn pin_instance_to_graph_node(&self, pin_inst: &PinInstRef<'_, N>) -> NodeIndex

fn create_delay_edges_intra_cell<D>( &mut self, inst: &CellInstRef<'_, N>, delay_model: &D )where D: CellDelayModel<N, Delay = T::Delay>,

fn create_constraint_edges<C>( &mut self, inst: &CellInstRef<'_, N>, constraint_model: &C )where C: CellConstraintModel<N, Constraint = T::Constraint>,

fn create_primary_input(&mut self, primary_input: TerminalId<N>)

Create a directed edge from the AAT source node the primary input nodes.

fn create_primary_input_delay_arcs(&mut self, top_cell: &CellRef<'_, N>)

Create directed edges from the AAT source node all primary input nodes.

Trait Implementations

impl<N: Debug + NetlistIds, T: Debug + ConstraintBase> Debug for TimingGraph<N, T>

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.