Trait libreda_sta::traits::timing_library::TimingLibrary

source · 
pub trait TimingLibrary {
    // Required methods
    fn get_slew(
        &self,
        edge_polarity: EdgePolarity,
        cell: &str,
        output_pin: &str,
        related_pin: &str,
        input_slew: Time,
        output_capacitance: Capacitance
    ) -> Option<Time>;
    fn get_cell_delay(
        &self,
        edge_polarity: EdgePolarity,
        cell: &str,
        output_pin: &str,
        related_pin: &str,
        input_slew: Time,
        output_capacitance: Capacitance
    ) -> Option<Time>;
    fn get_hold_constraint(
        &self,
        cell: &str,
        constrained_pin: &str,
        related_pin: &str,
        constrained_edge_polarity: EdgePolarity,
        related_edge_polarity: EdgePolarity,
        input_slew: Time,
        constrained_pin_transition: Time,
        output_capacitance: Capacitance
    ) -> Option<Time>;
    fn get_setup_constraint(
        &self,
        cell: &str,
        constrained_pin: &str,
        related_pin: &str,
        constrained_edge_polarity: EdgePolarity,
        related_edge_polarity: EdgePolarity,
        input_slew: Time,
        constrained_pin_transition: Time,
        output_capacitance: Capacitance
    ) -> Option<Time>;
}
Expand description

Query cell delays and setup/hold constraints.

Required Methods§

source

fn get_slew( &self, edge_polarity: EdgePolarity, cell: &str, output_pin: &str, related_pin: &str, input_slew: Time, output_capacitance: Capacitance ) -> Option<Time>

Get the transition time (slew) of an output pin. The transition time is dependent on the input transition time input_slew and the capacitive load at the output pin output_capacitance.

source

fn get_cell_delay( &self, edge_polarity: EdgePolarity, cell: &str, output_pin: &str, related_pin: &str, input_slew: Time, output_capacitance: Capacitance ) -> Option<Time>

Get the signal propagation time from the related_pin to the output_pin. The delay is dependent on the input transition time input_slew and the capacitive load at the output pin output_capacitance.

source

fn get_hold_constraint( &self, cell: &str, constrained_pin: &str, related_pin: &str, constrained_edge_polarity: EdgePolarity, related_edge_polarity: EdgePolarity, input_slew: Time, constrained_pin_transition: Time, output_capacitance: Capacitance ) -> Option<Time>

Get the a constraint between edges of two input signals. The ‘constrained’ edge is usually some data signal with is constrained by a clock signal (also called ‘related’ edge).

  • constrained_edge_polarity: Polarity of the constrained edge.
  • edge_polarity: Polarity of the related edge.
source

fn get_setup_constraint( &self, cell: &str, constrained_pin: &str, related_pin: &str, constrained_edge_polarity: EdgePolarity, related_edge_polarity: EdgePolarity, input_slew: Time, constrained_pin_transition: Time, output_capacitance: Capacitance ) -> Option<Time>

Get the a constraint between edges of two input signals. The ‘constrained’ edge is usually some data signal with is constrained by a clock signal (also called ‘related’ edge).

  • constrained_edge_polarity: Polarity of the constrained edge.
  • edge_polarity: Polarity of the related edge.

Implementors§