Expand description

ASIC place-and-route framework.

This crate contains interface definitions for place-and-route related algorithms.

The core idea of the framework is to enable independent development of place & route engines which then can easily be plugged together.


Incomplete overview:

  • place - interfaces for placement engines and representations of placement problems
  • rebuffer - interface for buffer insertion engines
  • route - interfaces for routing engines
  • timing_analysis - interfaces for static timing-analysis (STA) engines
  • util - useful functions which don’t yet have their own category


Implementations of place and route algorithms are not included in this crate. Some can be found in the following list:

Placement and legalizaton



pub use libreda_db;


The prelude helps to import most commonly used modules.

A Design structure collects information necessary for the place and route steps. This includes the netlist and layout, properties of cell instances, etc. Between Design structures and place & route engines lies an abstraction layer made by traits such as PlacementProblem.

Interface definitions for legalization engines (also known as detail placement).

Metrics and statistics for evaluating placement & routing quality.

Interface definitions for placement related algorithms.

Shortcut to most things defined in this crate.

Trait definitions for re-buffering of high-fanout nets. This includes clock-tree and buffer-tree generators.

Interface definitions for routing related algorithms.

test_data 🔒

Generate test data.

Interfaces for timing analysis engines.

Collection of utility functions.