1. Introduction
  2. 1. Database
    1. 1.1. Hierarchy
    2. 1.2. Netlist
    3. 1.3. Layout
    4. 1.4. Fused Netlist & Layout
    5. 1.5. Reference Access
  3. 2. Geometry
    1. 2.1. Euclidean Geometry
    2. 2.2. Boolean Operations
    3. 2.3. Region Queries
  4. 3. Logic
    1. 3.1. BDD
  5. PDKs
  6. 4. Introduction
    1. 4.1. OpenSource PDKs
  7. Library
  8. 5. Introduction
    1. 5.1. Generate Standard-Cells
    2. 5.2. Generate Memory-Macros
  9. I/O & File Formats
  10. 6. File formats
    1. 6.1. LEF/DEF
    2. 6.2. OASIS
    3. 6.3. Verilog
    4. 6.4. Liberty
  11. Physical Synthesis
  12. 7. Introduction
  13. 8. Floorplan
    1. 8.1. Power Routing
    2. 8.2. Well Taps
    3. 8.3. IO Pads
  14. 9. Placement
    1. 9.1. Global Placement
    2. 9.2. Legalization
  15. 10. Buffer & tie-cell insertion
  16. 11. Routing
    1. 11.1. Maze Routing
    2. 11.2. Conflict Resolution
      1. 11.2.1. Rip-up & Reroute
      2. 11.2.2. Negotiation Based Algorithms
    3. 11.3. Hierarchical Routing
      1. 11.3.1. Global Routing
      2. 11.3.2. Resource Estimation
      3. 11.3.3. Multilevel Full-Chip Routing
    4. 11.4. Line-Probe Algorithms
  17. 12. Clock-Tree Synthesis
  18. 13. Timing Driven Place & Route
    1. 13.1. Static Timing Analysis
      1. 13.1.1. Wire Delay Estimation
    2. 13.2. Timing Driven Placement
    3. 13.3. Hold Time Fixing
    4. 13.4. Timing Optimization Strategies
  19. Verification
  20. 14. Netlist Extraction
  21. 15. Netlist Comparison
  22. Design For Test (DFT)
  23. 16. Scan-Chain Insertion
  24. 17. Automated Test-Pattern Generation
  25. Appendix

LibrEDA Book

ATPG

See wikipedia.