Introduction
1.
Database
1.1.
Hierarchy
1.2.
Netlist
1.3.
Layout
1.4.
Fused Netlist & Layout
1.5.
Reference Access
2.
Geometry
2.1.
Euclidean Geometry
2.2.
Boolean Operations
2.3.
Region Queries
3.
Logic
3.1.
BDD
PDKs
4.
Introduction
4.1.
OpenSource PDKs
Library
5.
Introduction
5.1.
Generate Standard-Cells
5.2.
Generate Memory-Macros
I/O & File Formats
6.
File formats
6.1.
LEF/DEF
6.2.
OASIS
6.3.
Verilog
6.4.
Liberty
Physical Synthesis
7.
Introduction
8.
Floorplan
8.1.
Power Routing
8.2.
Well Taps
8.3.
IO Pads
9.
Placement
9.1.
Global Placement
9.2.
Legalization
10.
Buffer & tie-cell insertion
11.
Routing
11.1.
Maze Routing
11.2.
Conflict Resolution
11.2.1.
Rip-up & Reroute
11.2.2.
Negotiation Based Algorithms
11.3.
Hierarchical Routing
11.3.1.
Global Routing
11.3.2.
Resource Estimation
11.3.3.
Multilevel Full-Chip Routing
11.4.
Line-Probe Algorithms
12.
Clock-Tree Synthesis
13.
Timing Driven Place & Route
13.1.
Static Timing Analysis
13.1.1.
Wire Delay Estimation
13.2.
Timing Driven Placement
13.3.
Hold Time Fixing
13.4.
Timing Optimization Strategies
Verification
14.
Netlist Extraction
15.
Netlist Comparison
Design For Test (DFT)
16.
Scan-Chain Insertion
17.
Automated Test-Pattern Generation
Appendix
Light (default)
Rust
Coal
Navy
Ayu
LibrEDA Book
ATPG
See
wikipedia
.